ASIC Verification - mor research and technology consulting service

MOR-RTCS provides the experienced contractor for the ASIC verification service in the Bay Area. All contrators from MOR-RTCS earned Electronic Engineer M.S. degree in U.S. and received well trainings in the ASIC verification methodology. If you need a contract based enginner to expedite your ASIC verification project, here is the opportunity to utilize the experienced contractor for the following ASIC verification service :

1. Chip/Block level RTL/Gate sim using Synopsys VCS with SDF
2. Chip/Block level fomal verification using Cadence comformal tool
3. IP level for SerDes verification (LSI, Avago SerDes)
4. System/Chip level bring up using TCL for co-simulation
5. Chip/Block level static timing analysis (STA) using Synopsys PrimeTime
6. Chip/Block level clock tree analysis using Synopsys SpyGlass